1. Field of the Invention
The present invention is directed to an apparatus for producing an asynchronous, noncontinuous video clock for a document scanner and scanner data processing device and, more particularly, to a scanner which sends pixel data to the processing device in groups corresponding to the sensors in the scanner and also sends a video clock with multiple edges for each pixel only when the pixel data is being sent.
2. Description of the Related Art
Conventionally a scanner for a facsimile machine, as illustrated in FIG. 1, includes a contact array of multiple sensors 10 which scan a document 12 through scanning optics 14. FIG. 1 shows four sensors 10 however, for convenience and ease of description the drawings and discussion herein will discuss two sensors where each sensor has only two pixels since the same operations with respect to more than two pixels within a sensor and more than two sensors can be extrapolated. The electronics in the conventional scanner remove the overlapping pixels, concatenate the pixels and transmit the output as video signals as illustrated in FIG. 2. The data transmission starts with a horizontal synchronization signal pulse 16 which initiates a continuous video clock signal (VC). The video clock signal clocks or produces pulses 17 for an initial period 18 called a front porch period. The front porch period is a variable number of dummy pixel outputs. Then in synchronism with this previously started video clock, the pixel data (P1 and P2) for the first sensor is sent 20, followed by sending 22 the pixel data (P3 and P4) for the second sensor. The conventional video clock signal has only a single rising and falling edge per pixel as disclosed in U.S. Pat. No. 5,003,380. Subsequent to the transmission of the last of the pixel data is a back porch period 24 during which the video clock continues. Period 24 can be of any length. At this time another horizontal synchronization pulse 26 occurs signifying the end of transmission of a single video line from the scanner. The prior art requirement for sending the continuous video clock VC in front of and behind the actual sensor data requires complicated logic, see U.S. Pat. No. 4,905,085, on the video data reception side to properly recognize when the pixel data for each sensor is present on the data bus. This logic includes a phased lock loop circuit, a local oscillator and front and back porch clock strip logic.